The present invention generally relates to pulse width modulation of an electronic signal, and more specifically, to a programmable circuit for pulse width modulation of a clock signal in an integrated circuit, for instance, for use in clocking an arrange such as static random-access memory (SRAM).
Integrated circuits are used for a diverse number of electronic applications, from simple devices such as wristwatches to the most complex computer systems. Integrated circuits rely on a variety of clock signals to ensure proper circuit performance, but timing closure is becoming more difficult with each technology node used for integrated circuit design, such as for the 65 nanometer semiconductor device fabrication node.
There is an additional challenge for the circuit designer in constructing clock circuits that use reduced power. Low power circuits are becoming more prevalent due to power consumption problems. In particular, power dissipation has become a limiting factor for the yield of high performance circuit designs (operating at frequencies around one gigahertz or more) fabricated in deep sub micrometer technologies. Clock nets can contribute up to 50% of the total active power in multi-GHz designs. Low power designs are also preferable, since they exhibit less power supply noise and provide better tolerance with regard to manufacturing variations.
A typical clock control system has a pulsed clock generation circuit (e.g., a phase-lock loop) that generates a master clock signal. The master clock signal is fed to a clock distribution network that renders synchronized global clock signals at clock distribution structures such as local clock buffers (LCBs). Each LCB adjusts the global clock duty cycle and edges to meet the requirements of respective circuit elements, for example, local logic circuits, latches or memory arrays. A significant timing component in the SRAM control is the local clock signal pulse width, which determines SRAM read and write time windows.
U.S. Pat. No. 7,936,638 B2 addresses the local clock signal pulse width and proposes an electrical circuit comprising an input line adapted to receive an input signal switching binary states, an output line providing an output signal switch binary states responsive to the input line, a plurality of programmable paths connecting the output line to ground connections, wherein the programmable paths provide different pulldown rates, and means for selecting a desired one of the programmable paths based on a plurality of encoded control signals without using a separable decoder circuit, the selecting means including decode logic integrated with said programmable paths.
As technology advances and approaches the 14 nanometer semiconductor device fabrication node, further improvement in pulse width control with reduced or minimum control overhead to save chip area and power would be desirable.